Gesytec HD-PLC Core

We implemented the HD-PLC technology without using any Echelon components or software. It is a combination of Megachips HD-PLC technology and Gesytec EPOS LON stack. Over the span of 10 years, Gesytec self-developed EPOS stack has been used in tens of thousands of our products together with our own transceiver. EPOS has been an ideal solution for realizing a LON node with HD-PLC as it is designed to use in systems with few resources.

MegaChip's KHM1501 HD-PLC chip runs the LON protocol stack, which is powered by a cost-effective Cortex M0 CPU, a STM32F901 from ST, over a serial interface. The Cortex M0 CPU takes care of actual application and operates the peripherals. This separates the application from both the LON Stack and HD-PLC and avoids unwanted interactions. Ultimately, the application CPU can be chosen according to the requirements of each task to be solved.

The HD-PLC standard core of Gesytec provides these signals:

 

Row-ARow-BComment
1DAC_OUT1DAC_OUT2analog out
2ADC_IN6ADC_IN7analog in
3GND-AVCC-Aanalog supply
4PA0PA1digital
5PA2PA3digital
6PB8PB9digital
7PB10PB11digital
8PB12PB13digital
9PB14PB15digital
10GNDVCCdigital supply
11SWDIOSWCLKARM Debug
12GNDResetARM Debug
13UART5_TXResetdiagnostics

The digital signals can be used to implement serial protocols such as UART, SPI, I2C and CAN.